This invention relates to information processing systems, and more particularly to processing elements in such systems. Even more particularly, this invention relates to means for fetching instructions from a code store, such as main memory, into instruction decode logic of the processing element.
Any processing element within a computer must receive its instructions from some form of code store. Ideally, when the processing element is ready to execute the next instruction, that instruction would always be immediately available to its instruction decode logic so that the processing element would never have to wait for the instruction to be fetched. In slower processing systems, the code store is main memory, since the speed of main memory is fast enough to keep up with slower processors. As processor speed increases relative to main memory speed; processors will spend significant waiting time unless some form of high speed code buffer is placed between the processor and main memory.
The problem is further complicated by the requirement of branch instructions in the code, since these make the location of the next instruction unpredictable. Without branch instructions, the code buffer could be a simple first-in, first-out queue. However, because of branch instructions, the queue would need to be flushed and reloaded every time the processor encounters a branch instruction, which would not be very satisfactory. The longer the queue, the more time it would take to reload it. This approach would require only simple algorithms for loading instructions into and taking instructions from the queue; an instruction could be loaded whenever the queue is not full and an instruction could be taken whenever the queue is not empty.
One solution known for this problem is to make the code buffer a high speed random access memory (RAM) which would allow the next instruction to be accessed from any point in the code buffer. Addressing for this type of memory is done with a special memory called a content addressable memory (or sometimes called a translation lookaside buffer) so that the addresses in the high speed RAM appear the same as those in main memory. Only in the case of a branch to an instruction not currently in the RAM would the processing element have to wait for fetches from the main memory. For this approach, the algorithms for loading instructions into and taking instructions from the RAM are very complicated. They have to guarantee that the instructions being brought in do not overwrite instructions already in the buffer and that the instructions being executed are, in fact, the intended instructions.